Readings in Hardware/Software Co-Design

Giovanni De Micheli, Rolf Ernst, and Wayne Wolf, eds.

Morgan Kaufman Systems-on-Silicon Series

 

This page presents a list of papers on hardware/software co-design that have appeared since the Readings book was published. This list supplements the additional reading list found in the book. Like that list, this list of papers is not meant to be definitive. Rather, it should be used as a starting point for further explorations of the discipline.

 

 

 

 

 

 

Specification

 

F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, Y. Watanabe, and G. Yang, “Concurrent execution semantics and sequential simulation algorithms for Metropolis meta-model,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 13-18.

 

A. Siebenborn, O. Bringmann, and W. Rosenstiel, “Worst-case performance analysis of parallel, communicating software processes,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 37-42.

 

Memory Optimizations

 

P. R. Panda, L. Semeria, and G. De Micheli. “Cache-efficient memory layout of aggregate data structures”. In Proc. International Symposium on System Synthesis, Montreal, Canada, October 2001, pp. 101-106.

 

Harry Dwyer and John Fernando,  “Establishing a tight bound on task interference in embedded system instruction caches,” in Proceedings, CASES 2001, ACM Press, 2001, pp. 8-14.

 

Jan Sjodin and Carl von Platen, “Storage allocation for embedded processors,” in Proceedings, CASES 2001, ACM Press, 2001, pp. 15-23.

 

Oren Avissar, Rajeev Barua, and Dave Stewart, “Heterogeneous memory management for embedded systems,” in Proceedings, CASES 2001, ACM Press, 2001, pp. 34-43.

 

Synthesis Algorithms

 

M. Jersak, K. Richter, R. Henia, R. Ernst, and F. Slomka, “Transformation of SDL specifications for system-level timing analysis,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 121-126.

 

Hyunok Oh and Soonhoi Ha, “Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 133-138.

 

Daler N. Rakhmatov and Sarma B. K. Vrudhula, “Hardware/software bipartitioning for dynamically reconfigurable systems,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 145-150.

 

 

Software Optimizations

 

Jianwen Zhu and Edward S. Rogers, Jr., “Color permutation: an iterative algorithm for memory packing,” in Proceedings, ICCAD 01, IEEE, 2001, pp. 380-83.

 

Prabhat Jain, Srinivas Devadas, Daniel Engels, and Larry Rudolph, “Software-assisted cache replacement mechanisms for embedded systems,” in Proceedings, ICCAD 01, IEEE, 2001.

 

Markus Lorenz, David Kottman, Steven Bashford, Ranier Leupers, and Peter Marwedel, “Optimized address assignment for DSPs with SIMD memory accesses,” in Proceedings, ASP-DAC 2001, IEEE, 2001, pp. 415-420.

 

I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and J. Ramanujam, “Morphable cache architectures: potential benefits,” in Proc. Workshop on Languages, Compilers, and Tools for Embedded Systems, Snow Bird, Utah, 2001.

 

Catherine H. Gebotys, “Utilizing memory bandwidth in DSP embedded processors,” in Proceedings, DAC 2001, ACM Press, 2001, pp. 347-352.

 

J. T. Russell, “Program slicing for codesign,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 91-96.

 

Low Power

 

Amit Sinha and Anantha P. Chandrakasan, “JouleTrack---a Web based tool for software energy profiling,” in Proceedings, DAC 2001, ACM, 2001, pp. 220-225.

 

M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, and A. Parikh. “ Dynamic management of scratch pad memory space,” In Proceedings, DAC 2001, Las Vegas, NV, 2001.

 

M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and H. S. Kim, “Towards an energy-aware iteration space tiling,”in Proc. Workshop on Languages, Compilers, and Tools for Embedded Systems, Vancouver, June 2000.

N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye, “ Energy driven integrated hardware-software optimizations using SimplePower”, In Proc. International Symposium on Computer Architecture, Vancouver, Canada, 2000. 

 

M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and W. Ye. “Influence of compiler optimizations on system power,” In Proc. ACM Design Automation Conference, Los Angeles, CA, June 2000.

 

Kanishka Lahiri, Anand Ragunhathan, and Sujit Dey, “Fast system-level power profiling for battery-efficient system design,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 157-162.

 

Jinfeng Liu, Pai H. Chou, and Nader Bagherzadeh, “Communication speed selection for embedded systems with networked voltage-scalable processors,” in Proceedings, CODES 02, IEEE Computer Society Press, 2002, pp. 169-174.