Verilog and VHDL from the chapters (zip file of everything):

Errata:

p. 103: Q2-8c. Use C = 0.9 fF/micron^2 (= 2.9 fF/unit square for a minimum-width wire), r = 4 Ohms/square.

p. 127, Example 3-6: A download cable can't be used in master serial mode.

p. 130: Q2-11. "minimum-resistance metal 1 wire" -> "minimum-width metal 1 wire"

p. 130: The truth table in Figure 3-11 is incorrect. Here is a (hopefully) correct truth table:

a0 a1 b0 b1 out
0 0 0 0 d0
0 0 0 1 d2
0 0 1 0 d2
0 0 1 1 d2
0 1 0 0 d0
0 1 0 1 d2
0 1 1 0 d2
0 1 1 1 d2
1 0 0 0 d0
1 0 0 1 d2
1 0 1 0 d2
1 0 1 1 d2
1 1 0 0 d1
1 1 0 1 d3
1 1 1 0 d3
1 1 1 1 d3